{"id":72,"date":"2018-04-10T16:44:19","date_gmt":"2018-04-10T16:44:19","guid":{"rendered":"http:\/\/ferrywahyuwibowo.my.id\/?p=72"},"modified":"2018-04-11T03:36:12","modified_gmt":"2018-04-11T03:36:12","slug":"model-struktural-untuk-adder","status":"publish","type":"post","link":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/72\/model-struktural-untuk-adder\/","title":{"rendered":"Model Struktural untuk Adder"},"content":{"rendered":"<p>Diagram Rangkaian Penjumlah Penuh (<em>Full Adder<\/em>) (lihat gambar 1)<\/p>\n<p><a href=\"https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik5.jpg\"><img loading=\"lazy\" class=\"aligncenter size-full wp-image-247\" title=\"logik5\" src=\"https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik5.jpg?w=468&amp;h=324\" sizes=\"(max-width: 468px) 100vw, 468px\" srcset=\"https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik5.jpg?w=468&amp;h=324 468w, https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik5.jpg?w=150&amp;h=104 150w, https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik5.jpg?w=300&amp;h=208 300w, https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik5.jpg 754w\" alt=\"\" width=\"468\" height=\"324\" data-attachment-id=\"247\" data-permalink=\"https:\/\/ferrywahyu.wordpress.com\/2012\/01\/28\/penjumlah-menggunakan-model-struktural-berbasis-vhdl-dalam-fpga\/logik5\/\" data-orig-file=\"https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik5.jpg?w=468&amp;h=324\" data-orig-size=\"754,523\" data-comments-opened=\"1\" data-image-meta=\"{&quot;aperture&quot;:&quot;0&quot;,&quot;credit&quot;:&quot;&quot;,&quot;camera&quot;:&quot;&quot;,&quot;caption&quot;:&quot;&quot;,&quot;created_timestamp&quot;:&quot;0&quot;,&quot;copyright&quot;:&quot;&quot;,&quot;focal_length&quot;:&quot;0&quot;,&quot;iso&quot;:&quot;0&quot;,&quot;shutter_speed&quot;:&quot;0&quot;,&quot;title&quot;:&quot;&quot;}\" data-image-title=\"logik5\" data-image-description=\"\" data-medium-file=\"https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik5.jpg?w=468&amp;h=324?w=300\" data-large-file=\"https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik5.jpg?w=468&amp;h=324?w=468\" \/><\/a><\/p>\n<p style=\"text-align: center;\">Gambar 1. Diagram <em>Full Adder<\/em><\/p>\n<p>Bagian ini akan menjelaskan beberapa tahapan, diantaranya :<\/p>\n<ul>\n<li>Membangun penjumlah penuh dari dua penjumlah separuh (<em>half adder<\/em>)<\/li>\n<li>Menggunakan VHDL perancangan model struktural<\/li>\n<li>Merealisasikan rancangan menggunakan perancangan hirarki (merancanga penjumlah separuh, menghubungkan beberapa penjumlah separuh, dan termasuk bebrapa logik tambahan)<\/li>\n<\/ul>\n<p><strong>Perancangan VHDL menggunakan <em>Component<\/em><\/strong><\/p>\n<ol>\n<li>Tentukan logik sub rangkaian (terdiri dari <em>component<\/em>) yang akan digunakan dalam perancangan hirarki.<\/li>\n<li>Definisikan antarmuka pada sub rangkaian, dengan cara menggunakan format yang sama dengan pernyataan <em>Entity<\/em>.<\/li>\n<li>Sub rangkaian dihubungkan menggunakan <em>wire<\/em>, dikenal sebagai <em>structural<\/em> VHDL.<\/li>\n<li>Pernyataan <em>architecture<\/em> untuk sub rangkaian dapat terdiri dalam <em>file<\/em> yang sama sebagai rancangan tingkat teratas atau dalam <em>file<\/em> yang terpisah. Jika terdiri dalam <em>file<\/em> yang terpisah, harus dikompile terlebih dahulu.<\/li>\n<\/ol>\n<p>Format pernyataan komponen dalam VHDL dituliskan sebagai,<\/p>\n<p>COMPONENT &lt;nama komponen&gt;<\/p>\n<p>PORT ( &lt;signal antarmuka&gt; :\u00a0 tipe mode ) ;<\/p>\n<p>END COMPONENT ;<\/p>\n<p>Awal penulisan <em>instantiation<\/em> komponen dapat dituliskan sebagai,<\/p>\n<p>&lt;nama <em>instance<\/em>&gt; : &lt;nama komponen&gt;<\/p>\n<p>PORT MAP ( &lt;nama port komponen&gt; =&gt; &lt;nama <em>signal<\/em>&gt; ) ;<\/p>\n<p>&lt;nama <em>instance<\/em>&gt; : &lt;nama komponen&gt;<\/p>\n<p>PORT MAP ( &lt;nama <em>signal<\/em>&gt; ) ;<\/p>\n<p>Diagram skematik ditunjukkan pada gambar 2.<\/p>\n<p style=\"text-align: center;\"><a href=\"https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik6.jpg\"><img loading=\"lazy\" class=\"aligncenter size-full wp-image-248\" title=\"logik6\" src=\"https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik6.jpg?w=468&amp;h=141\" sizes=\"(max-width: 468px) 100vw, 468px\" srcset=\"https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik6.jpg?w=465&amp;h=141 465w, https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik6.jpg?w=150&amp;h=45 150w, https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik6.jpg?w=300&amp;h=91 300w, https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik6.jpg?w=768&amp;h=233 768w, https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik6.jpg 884w\" alt=\"\" width=\"468\" height=\"141\" data-attachment-id=\"248\" data-permalink=\"https:\/\/ferrywahyu.wordpress.com\/2012\/01\/28\/penjumlah-menggunakan-model-struktural-berbasis-vhdl-dalam-fpga\/logik6\/\" data-orig-file=\"https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik6.jpg?w=468&amp;h=141\" data-orig-size=\"884,268\" data-comments-opened=\"1\" data-image-meta=\"{&quot;aperture&quot;:&quot;0&quot;,&quot;credit&quot;:&quot;&quot;,&quot;camera&quot;:&quot;&quot;,&quot;caption&quot;:&quot;&quot;,&quot;created_timestamp&quot;:&quot;0&quot;,&quot;copyright&quot;:&quot;&quot;,&quot;focal_length&quot;:&quot;0&quot;,&quot;iso&quot;:&quot;0&quot;,&quot;shutter_speed&quot;:&quot;0&quot;,&quot;title&quot;:&quot;&quot;}\" data-image-title=\"logik6\" data-image-description=\"\" data-medium-file=\"https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik6.jpg?w=468&amp;h=141?w=300\" data-large-file=\"https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik6.jpg?w=468&amp;h=141?w=468\" \/><\/a>Gambar 2. Skematik <em>Adder<\/em><\/p>\n<p>VHDL untuk <em>entity<\/em> penjumlah penuhnya :<\/p>\n<p>LIBRARY ieee ;<\/p>\n<p>USE ieee.std_logic_1164.all ;<\/p>\n<p>ENTITY fulladd IS<\/p>\n<p>PORT ( Cin, A, B : \u00a0 IN \u00a0 STD_LOGIC ;<\/p>\n<p>Sum, Cout : \u00a0 OUT \u00a0 STD_LOGIC ) ;<\/p>\n<p>END fulladd ;<\/p>\n<p>Gambar 3 menunjukkan identitas dari <em>architecture<\/em> penjumlah penuh,<\/p>\n<p style=\"text-align: center;\"><a href=\"https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik7.jpg\"><img loading=\"lazy\" class=\"aligncenter size-full wp-image-249\" title=\"logik7\" src=\"https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik7.jpg?w=468&amp;h=209\" sizes=\"(max-width: 468px) 100vw, 468px\" srcset=\"https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik7.jpg?w=466&amp;h=209 466w, https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik7.jpg?w=150&amp;h=67 150w, https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik7.jpg?w=300&amp;h=134 300w, https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik7.jpg 598w\" alt=\"\" width=\"468\" height=\"209\" data-attachment-id=\"249\" data-permalink=\"https:\/\/ferrywahyu.wordpress.com\/2012\/01\/28\/penjumlah-menggunakan-model-struktural-berbasis-vhdl-dalam-fpga\/logik7\/\" data-orig-file=\"https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik7.jpg?w=468&amp;h=209\" data-orig-size=\"598,268\" data-comments-opened=\"1\" data-image-meta=\"{&quot;aperture&quot;:&quot;0&quot;,&quot;credit&quot;:&quot;&quot;,&quot;camera&quot;:&quot;&quot;,&quot;caption&quot;:&quot;&quot;,&quot;created_timestamp&quot;:&quot;0&quot;,&quot;copyright&quot;:&quot;&quot;,&quot;focal_length&quot;:&quot;0&quot;,&quot;iso&quot;:&quot;0&quot;,&quot;shutter_speed&quot;:&quot;0&quot;,&quot;title&quot;:&quot;&quot;}\" data-image-title=\"logik7\" data-image-description=\"\" data-medium-file=\"https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik7.jpg?w=468&amp;h=209?w=300\" data-large-file=\"https:\/\/ferrywahyu.files.wordpress.com\/2012\/01\/logik7.jpg?w=468&amp;h=209?w=468\" \/><\/a>Gambar 3. <em>Full Adder<\/em><\/p>\n<p>VHDL dari rangkaian gambar 3 sebagaimana berikut :<\/p>\n<p>ARCHITECTURE Struktur OF fulladd IS<\/p>\n<p>SIGNAL s1, c1, c2:\u00a0 STD_LOGIC ;<\/p>\n<p>COMPONENT halfadd<\/p>\n<p>PORT ( A, B :\u00a0 IN \u00a0 STD_LOGIC ;<\/p>\n<p>Sum, Cout : \u00a0 OUT \u00a0 STD_LOGIC ) ;<\/p>\n<p>END COMPONENT ;<\/p>\n<p>BEGIN<\/p>\n<p>ha1 : halfadd PORT MAP ( A =&gt; A, B =&gt; B, Sum =&gt; s1, Cout =&gt; c1 ) ;<\/p>\n<p>ha2 : halfadd PORT MAP ( A, B, Sum, c2 );<\/p>\n<p>Cout &lt;= c1 OR c2 ;<\/p>\n<p>END ;<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Diagram Rangkaian Penjumlah Penuh (Full Adder) (lihat gambar 1) Gambar 1. Diagram Full Adder Bagian ini akan menjelaskan beberapa tahapan, diantaranya : Membangun penjumlah penuh dari dua penjumlah separuh (half adder) Menggunakan VHDL perancangan model struktural Merealisasikan rancangan menggunakan perancangan hirarki (merancanga penjumlah separuh, menghubungkan beberapa penjumlah separuh, dan termasuk bebrapa logik tambahan) Perancangan VHDL [&hellip;]<\/p>\n","protected":false},"author":1,"featured_media":73,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":[],"categories":[6],"tags":[9,7,10,8],"_links":{"self":[{"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/posts\/72"}],"collection":[{"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/comments?post=72"}],"version-history":[{"count":1,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/posts\/72\/revisions"}],"predecessor-version":[{"id":74,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/posts\/72\/revisions\/74"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/media\/73"}],"wp:attachment":[{"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/media?parent=72"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/categories?post=72"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/tags?post=72"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}