{"id":54,"date":"2018-04-10T16:11:51","date_gmt":"2018-04-10T16:11:51","guid":{"rendered":"http:\/\/ferrywahyuwibowo.my.id\/?p=54"},"modified":"2018-04-11T03:36:35","modified_gmt":"2018-04-11T03:36:35","slug":"ripple-carry-adder","status":"publish","type":"post","link":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/54\/ripple-carry-adder\/","title":{"rendered":"Ripple Carry Adder"},"content":{"rendered":"

Diagram ripple carry<\/em> ditunjukkan pada gambar 1.<\/p>\n

\"\"<\/a><\/p>\n

Gambar 1. Ripple Carry<\/p>\n

secara khusus dapat digambarkan menurut gambar 2.<\/p>\n

\"\"<\/a>Gambar 2. Blok Ripple Carry<\/p>\n

Sehingga dengan mengasumsikan full adder<\/em> yang dibentuk secara struktural dari beberapa half adder<\/em> maka VHDL dari ripple carry<\/em> ini sebagaimana berikut,<\/p>\n

library ieee;<\/p>\n

use ieee.std_logic_1164.all;<\/p>\n

use work.pack.all<\/span>;<\/p>\n

ENTITY addbit IS<\/p>\n

PORT (a : \u00a0 IN \u00a0 std_logic_vector(2 downto 0);<\/p>\n

b : IN \u00a0 std_logic_vector(2 downto 0);<\/p>\n

cin : IN \u00a0 std_logic;<\/p>\n

s : \u00a0 OUT std_logic_vector(2 downto 0);<\/p>\n

cout : \u00a0 OUT \u00a0 std_logic);<\/p>\n

END;<\/p>\n

ARCHITECTURE struktural OF addbit IS<\/p>\n

SIGNAL cin1, cin2: std_logic;<\/p>\n

BEGIN<\/p>\n

fa0: fa PORT MAP(a(0),b(0), cin, s(0), cin1 );<\/p>\n

fa1: fa PORT MAP(a(1),b(1), cin1, s(1), cin2 );<\/p>\n

fa2: fa PORT MAP(a(2),b(2), cin2, s(2), cout );<\/p>\n

END;<\/p>\n

atau bisa juga menggunakan deskripsi architecture yang lebih singkat lagi, dengan cara menuliskan kode VHDL-nya sebagai berikut,<\/p>\n

ARCHITECTURE struktural OF addbit IS<\/p>\n

SIGNAL cy : std_logic_vector (3 downto 0);<\/p>\n

BEGIN<\/p>\n

Penjumlah:<\/p>\n

FOR i IN 0 TO 2 GENERATE<\/p>\n

myfa:fa PORT MAP(a(i),b(i),cy(i),s(i),cy(i+1));<\/p>\n

END GENERATE;<\/p>\n

cout <= cy(3);<\/p>\n

cy(0) <= cin;<\/p>\n

END;<\/p>\n

Rangkaian carry ripple<\/em> sangat lambat pewaktuannya karena banyaknya penyambungan per langkah blok rangkaian penjumlah separuhnya, sehingga untuk mengatasi hal ini bisa menggunakan metode pipelining<\/em>, retiming<\/em> atau dengan cara bus<\/em>. Namun, cara yang paling sering digunakan adalah pipelining<\/em>.<\/p>\n","protected":false},"excerpt":{"rendered":"

Diagram ripple carry ditunjukkan pada gambar 1. Gambar 1. Ripple Carry secara khusus dapat digambarkan menurut gambar 2. Gambar 2. Blok Ripple Carry Sehingga dengan mengasumsikan full adder yang dibentuk secara struktural dari beberapa half adder maka VHDL dari ripple carry ini sebagaimana berikut, library ieee; use ieee.std_logic_1164.all; use work.pack.all; ENTITY addbit IS PORT (a […]<\/p>\n","protected":false},"author":1,"featured_media":55,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":[],"categories":[6],"tags":[9,7,10,8],"_links":{"self":[{"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/posts\/54"}],"collection":[{"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/comments?post=54"}],"version-history":[{"count":1,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/posts\/54\/revisions"}],"predecessor-version":[{"id":56,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/posts\/54\/revisions\/56"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/media\/55"}],"wp:attachment":[{"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/media?parent=54"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/categories?post=54"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/tags?post=54"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}