{"id":180,"date":"2018-04-11T08:01:36","date_gmt":"2018-04-11T08:01:36","guid":{"rendered":"http:\/\/ferrywahyuwibowo.my.id\/?p=180"},"modified":"2018-04-12T11:56:28","modified_gmt":"2018-04-12T11:56:28","slug":"notes-for-fpga-designer","status":"publish","type":"post","link":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/180\/notes-for-fpga-designer\/","title":{"rendered":"Notes for FPGA Designer"},"content":{"rendered":"
    \n
  1. VHDL and Verilog are not a programming language<\/li>\n
  2. FPGA and CPLD don’t execute VHDL and Verilog<\/li>\n
  3. VHDL and Verilog are used to describe a behavioral of the required hardware<\/li>\n
  4. Execution of VHDL and Verilog known as synthesis not compile<\/li>\n
  5. Synthesis of VHDL and Verilog will be generated into logic by a tool<\/li>\n
  6. Always check the logic\/components required, verification of flip-flop count, if getting latches so there is a mistake in designing<\/li>\n
  7. Start designing from the simple modular\/block until implementation of component blocks<\/li>\n
  8. The tool will eliminate useless logics and ports<\/li>\n
  9. The tool of synthesis could justify a simple error<\/li>\n
  10. Simulator executes VHDL and Verilog without changing<\/li>\n
  11. VHDL and Verilog could be success simulated yet failed to result in logic in the hardware when it is implemented<\/li>\n<\/ol>\n

    In Indonesia:<\/strong><\/p>\n

      \n
    1. VHDL dan Verilog bukanlah bahasa pemrograman<\/li>\n
    2. FPGA dan CPLD tidak mengeksekusi VHDL dan Verilog<\/li>\n
    3. VHDL dan Verilog digunakan untuk mendeskripsikan watak perangkat keras yang diperlukan<\/li>\n
    4. Eksekusi VHDL dan Verilog disebut sebagai sintesis bukan kompile<\/li>\n
    5. Sintesis VHDL dan Verilog akan di-generate menjadi logik oleh tool<\/li>\n
    6. Selalu cek logik \/ komponen yang diperlukan, verifikasi cacah flip-flop, jika mendapatkan latch maka telah terjadi kesalahan dalam perancangan<\/li>\n
    7. Mulai perancangan dari modul \/ blok yang sederhana sampai implementasi blok-blok component<\/li>\n
    8. Tool akan menghilangkan logik dan port yang tidak berguna<\/li>\n
    9. Tool sintesis dapat membenarkan error yang sederhana<\/li>\n
    10. Simulator mengeksekusi VHDL dan Verilog tanpa merubahnya<\/li>\n
    11. VHDL dan Verilog dapat sukses disimulasikan tetapi gagal untuk menghasilkan logik dalam perangkat keras ketika diimplementasikan<\/li>\n<\/ol>\n

       <\/p>\n","protected":false},"excerpt":{"rendered":"

      VHDL and Verilog are not a programming language FPGA and CPLD don’t execute VHDL and Verilog VHDL and Verilog are used to describe a behavioral of the required hardware Execution of VHDL and Verilog known as synthesis not compile Synthesis of VHDL and Verilog will be generated into logic by a tool Always check the […]<\/p>\n","protected":false},"author":1,"featured_media":181,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":[],"categories":[6],"tags":[7,16,13,14,15,10,8],"_links":{"self":[{"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/posts\/180"}],"collection":[{"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/comments?post=180"}],"version-history":[{"count":4,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/posts\/180\/revisions"}],"predecessor-version":[{"id":209,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/posts\/180\/revisions\/209"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/media\/181"}],"wp:attachment":[{"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/media?parent=180"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/categories?post=180"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/tags?post=180"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}