{"id":165,"date":"2018-04-11T04:04:11","date_gmt":"2018-04-11T04:04:11","guid":{"rendered":"http:\/\/ferrywahyuwibowo.my.id\/?p=165"},"modified":"2018-04-11T04:04:11","modified_gmt":"2018-04-11T04:04:11","slug":"vhdl-menggunakan-xilinx-ise","status":"publish","type":"post","link":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/165\/vhdl-menggunakan-xilinx-ise\/","title":{"rendered":"VHDL Menggunakan Xilinx ISE"},"content":{"rendered":"

Penambahan proyek menggunakan masukan VHDL baru dapat dilakukan dengan memilih new source<\/em> di proyek, kemudian memilih jenis modul VHDL baru dan nama entity<\/em>.<\/p>\n

\"\"<\/a><\/p>\n

Desain yang dibuat untuk membuat keluaran 8 LED berkedip pada FPGA Spartan 3E Starter Kit secara berurutan. Clock<\/em> digunakan untuk men-trigger<\/em> sinyal agar berlaku proses sekuensial yang ditandai dengan keluaran LED. Frekuensi clock<\/em> yang terdapat pada FPGA Spartan 3E starter kit adalah 50 MHz (waktunya 20 ns), clock<\/em> ini kemudian akan di buat menjadi 1 detik dengan menambahkan clock divider<\/em>.<\/p>\n

\"\"<\/a>Pilih next<\/em>, kemudian akan muncul ringkasan dari proyek yang dibuat.<\/p>\n

\"\"<\/a><\/p>\n

VHDL yang dibuat dengan entity<\/em> di atas adalah:<\/p>\n

library IEEE;<\/address>\n
use IEEE.STD_LOGIC_1164.ALL;<\/address>\n
use IEEE.STD_LOGIC_ARITH.ALL;<\/address>\n
use IEEE.STD_LOGIC_UNSIGNED.ALL;<\/address>\n
\u2014- Uncomment the following library declaration if instantiating<\/address>\n
\u2014- any Xilinx primitives in this code.<\/address>\n
\u2013library UNISIM;<\/address>\n
\u2013use UNISIM.VComponents.all;<\/address>\n
entity Proyek is<\/address>\n
\u00a0\u00a0\u00a0 Port ( CLK : in\u00a0 STD_LOGIC;<\/address>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 LED : out\u00a0 STD_LOGIC_VECTOR (7 downto 0));<\/address>\n
end ;<\/address>\n
architecture Watak of Proyek is<\/address>\n
signal poin: STD_LOGIC_VECTOR(7 DOWNTO 0):=\u201d00000001\u2033;<\/address>\n
signal counter: INTEGER:=0;<\/address>\n
constant counter_max: INTEGER:=49999999;<\/address>\n
begin<\/address>\n
process (CLK) is \u2014 Pembagi clock<\/address>\n
begin<\/address>\n
if rising_edge(CLK) then<\/address>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 if counter<counter_max then<\/address>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 counter<=counter+1;<\/address>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 else<\/address>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 counter<=0;<\/address>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 end if;<\/address>\n
end if;<\/address>\n
end process;<\/address>\n
process (CLK) is<\/address>\n
begin<\/address>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 if clk\u2019EVENT and clk=\u20191\u2032 then<\/address>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 if counter=0 then<\/address>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 poin<=poin(6 downto 0)&poin(7);<\/address>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 end if;<\/address>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 end if;<\/address>\n
end process;<\/address>\n
\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0\u00a0 LED<=poin;<\/address>\n
end;<\/address>\n","protected":false},"excerpt":{"rendered":"

Penambahan proyek menggunakan masukan VHDL baru dapat dilakukan dengan memilih new source di proyek, kemudian memilih jenis modul VHDL baru dan nama entity. Desain yang dibuat untuk membuat keluaran 8 LED berkedip pada FPGA Spartan 3E Starter Kit secara berurutan. Clock digunakan untuk men-trigger sinyal agar berlaku proses sekuensial yang ditandai dengan keluaran LED. Frekuensi […]<\/p>\n","protected":false},"author":1,"featured_media":166,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":[],"categories":[6],"tags":[7,16,13,14,15,10,8],"_links":{"self":[{"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/posts\/165"}],"collection":[{"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/comments?post=165"}],"version-history":[{"count":1,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/posts\/165\/revisions"}],"predecessor-version":[{"id":167,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/posts\/165\/revisions\/167"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/media\/166"}],"wp:attachment":[{"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/media?parent=165"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/categories?post=165"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/ferrywahyuwibowo.my.id\/index.php\/wp-json\/wp\/v2\/tags?post=165"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}